In asynchronous transmission, data is coded into a series of pulses, including a start bit, and including a stop bit or a guard band. The start bit is sent by a sending unit to inform a receiving unit that a character is to be sent. The character is then sent, followed by the stop bit or guard band, designating that the transfer of that bit is complete. Modes of asynchronous communication are frequently defined in standards that are established by standards setting bodies, such as the American National Standards Institute (ANSI), the International Telecommunications Union (ITU) and the International Organization for Standardization (ISO).
Asynchronous communication is frequently used to transfer data to and from plug-in units, such as modems, memory cards, and the like, that are plugged into host units, such as digital cameras, personal computers, and the like. An interface controller in the host unit manages the asynchronous data communication between the plug-in unit and the host unit. An exemplary asynchronous communication standard is the ISO7816 standard, adopted by the ISO. Plug-in units communicating with an interface controller in a manner that complies with the ISO7816 standard are frequently referred to as Smart Cards, or Integrated Circuit Cards.
FIG. 1 shows a typical Smart Card interface arrangement. A Smart Card unit 10 is electrically connected to a host unit 14 by way of an interface controller 12 in the host unit 14 that manages the transfer of data between the Smart Card unit 10 and the host unit 14. The transfer of data between the host unit 14 and the interface controller 12 is shown by way of example in FIG. 1 as being by way of a PCI bus 16 in the host unit 14. Numerous other means for communicating data between the interface controller and the host unit are possible, including EISA bus, universal serial bus (USB), and so on. The Smart Card connection to the host unit 14 is by way of a two-way serial line 11, which is split in the host unit 14 into a transmitting line 26 and a receiving line 30, using well known techniques. The rate of data exchange between the Smart Card unit 10 and the interface controller 12 is controlled by an interface clock, which can be at one of five different clock frequencies, 4 MHz, 6 MHz, 8 MHz, 12 MHz and 20 MHz.
The interface unit 12 includes a Smart Card interface subunit 18 and a PCI interface subunit 20. The Smart Card interface subunit 18 includes a Smart Card block 22 and a parity checker block 24. The Smart Card block 22 receives the signals transmitted on line 26 by the Smart Card unit 10, recovers the data in those signals, and then sends that data on line 27 to the PCI interface subunit where it is placed on the PCI bus 16 according to the well-known PCI standard protocol, for transmission to other parts (not shown) of the host unit 14. The parity checker block 24 monitors the data on line 26 to detect whether a parity error exists in a character of data. If such a parity error is so detected, the parity checker block 24 asserts a signal on line 28, which causes a gate 29 to block the Smart Card block 22 from receiving the error, and sends a signal on line 30 to the Smart Card unit 10 notifying it of the error, which prompts an attempted re-send of the affected character from the Smart Card unit 10. Further details on this and other aspects of the ISO7816 standard can be found in the ISO7816 standard publication, which may be obtained from the International Organization for Standardization at 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland. A basic overview of the ISO7816 standard may be obtained from the Smart Card Industry Association at 191 Clarksville Road, Princeton Junction, N.J. 08550.
FIG. 2 is a timing diagram for a signal that is compliant with the ISO7816 standard, with time represented on the horizontal axis. A complete character is shown in the figure, starting at time 0 and ending at time tn. The character is composed of bits, each bit being of a defined duration referred to in the ISO7816 standard as an Elementary Time Unit, or etu. At any given time the signal is at either an A state or a Z state. At the beginning of a character, between time 0 and time t1, a start bit having a value of A is sent, followed by eight data bits between time t1 and time t9. The eight data bits are followed, between time t9 and t10, by a parity bit. The parity bit is followed by a guard time having a variable number of etus duration, between time t10 and the end of the character, time tn. The delay between two consecutive characters is at least 12 etu, including a character duration (10+/−0.2 etu), plus the guard time.
Referring again to FIG. 1, the parity checker block 24 monitors the data detected by the Smart Card block 22 to detect whether a parity error exists in a character of data. If such a parity error is so detected, the parity checker block 24 sends a signal on line 30 to the Smart Card unit 10 notifying it of the error, which prompts an attempted re-send of the affected character from the Smart Card unit 10. The detection of a parity error is also signaled in the data stream generated on line 27. Referring now to FIG. 9, the ISO7816 standard specifies that when a parity error is detected, during the guard time starting at 10.5+/−0.2 etu the receiver transmits an error signal at state A for 1 etu minimum and 2 etu maximum.
However, a problem exists in the above and similar arrangements in that the rate at which the signals are sampled in the interface unit 12 may be varied during operation, and a sampling delay introduced to the data. For example, referring again to the arrangement shown in FIG. 1, sometimes parity errors are detected in the parity checker block 24 because of the occurrence of glitches occurring on the signals sent from the Smart Card unit 10. In order to be able to be able to successfully detect the data in asynchronous communication, even if glitches are present, and also to avoid the time expenditure involved in parity error detecting and signaling, and re-send of data, it may be desirable to implement a glitch filter, for example of the type described in co-pending U.S. patent application Ser. No. (TI-34197). In that application, a glitch filter is implemented in which the width of glitches is determined, and a sample rate for the asynchronous data is varied, depending on the glitch width. However, the glitch filter introduces a sampling delay to the data. This delay shifts the assertion of the error signal, so that it may not be asserted within the specified time, i.e., beginning at 10.5+/−0.2 etu.
To avoid the delay, the parity checker in the Smart Card unit could be modified to sample the data before the glitch filter. However, this approach could result in a significant number of unnecessary parity errors being reported during operation of the Smart Card.
This problem is not limited to asynchronous data communicated according to the ISO7816 standard, but is a problem with respect to asynchronous data communication generally, wherein a specified signal must be asserted in a character of detected asynchronous data, and a variable delay is introduced in the sampling of the data. It would be desirable to be able to be able to vary the delay in the sampling of the data, while still being able to assert such specified signal at the proper time.